1. Field
The embodiments discussed herein are directed to a latch circuit having a clear function capable of clearing an output signal without being depended on by an externally inputted external signal, a flip-flop circuit including the latch circuit, and a logic circuit.
2. Description of the Related Art
FIG. 1 shows a circuit configuration of a conventional D flip-flop (DFF) circuit 101. As shown in FIG. 1, the DFF circuit 101 includes: a master circuit 110 disposed on the input-side and which constitutes a D latch circuit; and a slave circuit 112 disposed on the output-side and which constitutes a D latch circuit. The master circuit 110 has an input terminal connected to an input section 102 to which an external signal D is externally inputted and an output terminal connected to the input terminal of the slave circuit 112. The output terminal of the slave circuit 112 is connected to an output section 104 from which an output signal Q is outputted.
The master circuit 110 includes: a gated inverter circuit 103 whose input terminal is connected to the input section 102; and a state retaining circuit 106 whose input terminal is connected to the output terminal of the gated inverter circuit 103 and whose output terminal becomes the output terminal of the master circuit 110. The gated inverter circuit 103 is arranged so that output/non-output of a first inversion signal whose phase is inverted by 180 degrees with respect to the external signal D is switchable based on clock signals CLK, CLKX as control signals.
The state retaining circuit 106 includes an inverter circuit 105 and a gated inverter circuit 107. The first inversion signal is inputted from the gated inverter circuit 103 to the inverter circuit 105. In addition, the inverter circuit 105 is arranged to output a second inversion signal whose phase is inverted by 180 degrees with respect to the first inversion signal to the gated inverter circuit 107 and the slave circuit 112. The gated inverter circuit 107 is arranged so that output/non-output of a third inversion signal whose phase is inverted by 180 degrees with respect to the second inversion signal is switchable based on the clock signals CLK, CLKX.
The gated inverter circuit 107 operates so as to non-output/output the third inversion signal in synchronization with the output/non-output of the gated inverter circuit 103. Therefore, when the gated inverter circuit 103 is in a non-output state, the gated inverter circuit 107 connects a signal retaining path linking the input and output terminals of the inverter circuit 105. As a result, a latch loop is formed by the inverter circuit 105 and the gated inverter circuit 107 within the state retaining circuit 106. The first inversion signal inputted to the inverter circuit 105 and the third inversion signal outputted by the gated inverter circuit 107 are in phase with each other. Therefore, the state retaining circuit 106 continues to retain the state of the logical level of the second inversion signal as long as the latch loop is formed and the gated inverter circuit 103 is in a non-output state.
As shown in FIG. 1, the configuration of the slave circuit 112 is similar to that of the master circuit 110. The slave circuit 112 includes a gated inverter circuit 109 and a state retaining circuit 108. The gated inverter circuit 109 corresponds to the gated inverter circuit 103 of the master circuit 110, while the state retaining circuit 108 corresponds to the state retaining circuit 106 of the master circuit 110. The state retaining circuit 108 includes an inverter circuit 111 and a gated inverter circuit 113. The inverter circuit 111 corresponds to the inverter circuit 105 of the state retaining circuit 106. The gated inverter circuit 113 corresponds to the gated inverter circuit 107 of the state retaining circuit 106.
The second inversion signal outputted from the master circuit 110 is inputted to the gated inverter circuit 109. The inverter circuit 111 outputs a fourth inversion signal whose phase is inverted by 180 degrees with respect to the second inversion signal to the output section 104. The fourth inversion signal becomes the output signal Q.
FIG. 2 shows a circuit configuration of a conventional clear function-added DFF circuit 201. As shown in FIG. 2, the clear function-added DFF circuit 201 includes NOR circuits 115 and 117, having one of the respective terminals thereof connected to a clear input section 116 to which a clear signal CLR is inputted, in place of the inverter circuits 105 and 111 of the DFF circuit 101. When a high-level clear signal CLR is inputted, the clear function-added DFF circuit 201 is able to clear an output signal Q to a low level without being depended on by the logical level of an external signal D.
FIG. 3 shows a circuit configuration of a conventional clear function-added D latch circuit 301. As shown in FIG. 3, the clear function-added D latch circuit 301 includes: a gated inverter circuit 121 whose input terminal is connected to an input section 102 to which an external signal D is inputted; and a state retaining circuit 130 whose input terminal is connected to an output terminal of the gated inverter circuit 121 and whose output terminal is connected to an output section 104 from which an output signal Q is outputted. The state retaining circuit 130 includes a NOR circuit 123 having: one input terminal to which a clear signal CLR is inputted; another input terminal to which the output signal of the gated inverter circuit 121 is inputted; and an output terminal that becomes the output terminal of the state retaining circuit 130. The state retaining circuit 130 further includes a gated inverter circuit 125 having: an input terminal connected to the output terminal of the NOR circuit 123; and an output terminal connected to the input terminal of the NOR circuit 123.
The gated inverter circuit 121 includes p-type complimentary metal-oxide semiconductors (PMOSFETs) 131, 133 and n-type MOSFETs (NMOSFETs) 135, 137 connected in series between a power supply terminal to which a power supply voltage VDD is applied and a ground terminal that becomes a reference potential VSS. The external signal D is respectively inputted to gate terminals of the PMOSFET 131 and the NMOSFET 137. A clock signal CLK is inputted to a gate terminal of the PMOSFET 133. A clock signal CLKX is inputted to a gate terminal of the NMOSFET 135.
The NOR circuit 123 includes: PMOSFETs 141, 143 and an NMOSFET 145 connected in series between the power supply terminal and the ground terminal; and an NMOSFET 147 connected in parallel with the NMOSFET 145. The output signal of the gated inverter circuit 121 is respectively inputted to gate terminals of the PMOSFET 143 and the NMOSFET 145. The clear signal CLR is respectively inputted to gate terminals of the PMOSFET 141 and the NMOSFET 147.
The gated inverter circuit 125 includes PMOSFETs 151, 153 and NMOSFETs 155, 157 connected in series between the power supply terminal and the ground terminal. The output signal of the NOR circuit 123 is respectively inputted to gate terminals of the PMOSFET 151 and the NMOSFET 157. The clock signal CLKX is inputted to a gate terminal of the PMOSFET 153 while the clock signal CLK is inputted to a gate terminal of the NMOSFET 155.
At the clear function-added D latch circuit 301, when a high-level clear signal CLR is inputted, the PMOSFET 141 changes to an off-state and disconnects the connection between the power supply terminal and the output terminal of the NOR circuit 123, and the NMOSFET 147 changes to an on-state and connects the output terminal of the NOR circuit 123 with the ground terminal. As a result, the output signal Q is cleared to a low level without being depended on by the logical level of the external signal D.
FIG. 4 shows another circuit configuration of a conventional clear function-added DFF circuit 201. The clear function-added DFF circuit 201 shown in FIG. 4 includes: transfer gate circuits 161, 171 in place of the gated inverter circuits 103, 109 of the clear function-added DFF circuit 201 shown in FIG. 2; and NAND circuits 163, 173 respectively having one input terminal to which a clear signal CLR is inputted in place of the NOR circuits 115, 117. Furthermore, the clear function-added DFF circuit 201 shown in FIG. 4 includes: a transfer gate circuit 165 and an inverter circuit 167 in place of the gated inverter circuit 107 of the clear function-added DFF circuit 201 shown in FIG. 2; and a transfer gate circuit 175 and an inverter circuit 177 in place of the gated inverter circuit 113.
As shown in FIG. 4, output terminals of the NAND circuits 163, 173 are respectively connected to the input terminals of the inverter circuits 167, 177. Output terminals of the inverter circuits 167, 177 are respectively connected to input terminals of the transfer gate circuits 165, 175. Output terminals of the transfer gate circuits 165, 175 are respectively connected to the other input terminals of the NAND circuits 163, 173.
At the clear function-added DFF circuit 201, when a low-level clear signal CLR is inputted, the output signals of the NAND circuits 163, 173 assume a constant high logical level. As a result, the output signal Q may be cleared to a high level regardless of the logical level of the external signal D.
FIG. 5 shows another circuit configuration of a conventional clear function-added D latch circuit 301. The clear function-added D latch circuit 301 shown in FIG. 5 includes: a transfer gate circuit 181 in place of the gated inverter circuit 121 of the clear function-added D latch circuit 301 shown in FIG. 3; and a NAND circuit 183 having one input terminal to which a clear signal CLR is inputted in place of the NOR circuit 123. In addition, the clear function-added D latch circuit 301 shown in FIG. 5 includes a transfer gate circuit 185 and an inverter circuit 187 in place of the gated inverter circuit 125 of the clear function-added D latch circuit 301 shown in FIG. 3.
The transfer gate circuit 181 includes a PMOSFET 191 and an NMOSFET 193 connected in parallel. A clock signal CLK is inputted to the gate terminal of the PMOSFET 191, while a clock signal CLKX is inputted to the gate terminal of the NMOSFET 193. Source terminals of the PMOSFET 191 and the NMOSFET 193 are connected to each other, and an external signal D is inputted thereto. Drain terminals of the PMOSFET 191 and the NMOSFET 193 are connected to each other, and an output signal is outputted therefrom.
The NAND circuit 183 includes: a PMOSFET 213 and NMOSFETs 215, 217 connected in series between the power supply terminal and the ground terminal; and a PMOSFET 211 connected in parallel with the PMOSFET 213. The output signal of the transfer gate circuit 181 is respectively inputted to gate terminals of the PMOSFET 213 and the NMOSFET 215. The clear signal CLR is respectively inputted to gate terminals of the PMOSFET 211 and the NMOSFET 217.
The inverter circuit 187 includes a PMOSFET 221 and an NMOSFET 223 connected in series between the power supply terminal and the ground terminal. The output signal of the NAND circuit 183 is inputted to gate terminals of the PMOSFET 221 and the NMOSFET 223. An inversion signal is outputted from drain terminals of the PMOSFET 221 and the NMOSFET 223.
The transfer gate circuit 185 includes a PMOSFET 195 and an NMOSFET 197 connected in parallel. A clock signal CLKX is inputted to a gate terminal of the PMOSFET 195. A clock signal CLK is inputted to a gate terminal of the NMOSFET 197. Source terminals of the PMOSFET 195 and the NMOSFET 197 are mutually connected and are connected to the output terminal of the inverter circuit 187, while drain terminals thereof are mutually connected and are connected to the other input terminal of the NAND circuit 183.
At the clear function-added D latch circuit 301, when a low-level clear signal CLR is inputted, the NMOSFET 217 changes to an off-state and disconnects the connection between the ground terminal and the output terminal of the NOR circuit 123, and the PMOSFET 211 changes to an on-state and connects the output terminal of the NOR circuit 123 with the power supply terminal. As a result, an output signal Q is cleared to a high level without being depended on by the logical level of an external signal D.